An open drain bus, such as an Inter-Integrated Circuit bus, a System Management Bus (SMBus) and others, includes a data line and a clock line. The Inter-Integrated Circuit bus is often referred to as an IIC, I2C or I2C bus, and is hereinafter referred to as an I2C bus. The data line and the clock line can each be referred to individually as a bus line, or simply as a line. Each of the bus lines is connected to a pull-up resistor, interface devices and a capacitance representing distributed capacitance of the bus line and the total input capacitance of the connected interface devices. The data transfer rate depends upon the speed at which the resistor can charge the capacitance.
I2C buses are used in a variety of implementations, including those involving servers and computers, with applications including system monitoring and configuration. However, the I2C pins on certain devices, such as processors and ASICS, often use GPIO pins with high drive strength and no edge rate control. These approaches can result in problems with overshoot and noise, as may be applicable, for example, to falling rates at transitions that are less than the round trip time for the I2C bus. Related issues may arise in connection with the reflection of waves off of the end of the bus, which can result in turning on of clamp/body diodes on parts distributed along the bus. Other issues may also arise in compensating for fast transitions, as other characteristics of I2C bus communications can be affected, such as those limiting the voltage level that can be used to drive the bus to a logic low.
The implementation of various disparate devices with I2C busses, and of edge rate suppression for such devices, continues to be challenging in view of the above and other issues.